Asynchronous Control Logic Modelization - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

The clock event statement occurs after the modelization of any asynchronous control logic (asynchronous set/reset).

In the if branch of the clock event, the modelization of the synchronous logic (data, optional synchronous set/reset, optional clock enable) is done.

Table 1. Asynchronous Control Logic Modelization Summary
Modelization Type Contains Performed
Asynchronous control logic Asynchronous set/reset Before the clock event statement
Synchronous logic

Data

Optional synchronous set/reset

Optional clock enable

In the clock event if branch.