Arrays Example Two - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

This coding example describes an array of 64 8-bit wide elements. You can assign these elements only in structural Verilog code.

wire [7:0] mem_array [63:0];