Arrays Example Two - Arrays Example Two - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2026-07-08
Version
2026.1 English

This coding example describes an array of 64 8-bit wide elements. You can assign these elements only in structural Verilog code.

wire [7:0] mem_array [63:0];