ASYNC_REG - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

The ASYNC_REG is an attribute that affects many processes in the Vivado tool flow. This attribute informs the tool whether the register can receive asynchronous data on its D input pin relative to the source clock. Alternatively, it indicates that the register is a synchronizing register within a synchronization chain. Vivado synthesis treats it as a DONT_TOUCH attribute and pushes the ASYNC_REG property forward in the netlist. This process ensures that the synchronizing chain of registers tagged with ASYNC_REG remain intact throughout the implementation flow.

For information on how other Vivado tools handle this attribute, see Vivado Design Suite Properties Reference Guide (UG912).

You can place this attribute on any register; values are FALSE (default) and TRUE. You can set this attribute in RTL or XDC

Important: You must be careful when putting this attribute on loadless signals. The system may not preserve the attribute and signal. Attributes are case-insensitive, regardless of HDL.