Create a test bench for a design unit instance. This command creates a functional system Verilog-based test bench for the scoped hierarchical instance. The test bench defines the selected instance as a Design Under Test (DUT). It includes details such as, port/signal specification, parameter declaration, stimuli vector include file, and module instantiation of the DUT. This command allows you to add the test bench to an existing or a new simulation fileset from which the simulation can be launched.
| Option | Description |
|---|---|
-name <arg>
|
Specify the name of the test bench module name. The default name is test bench. |
-add_to_simset <arg>
|
Specify simulation fileset name to which the test bench needs to be added. If this switch is not specified, then the command adds a test bench to the current active simulation fileset. |
-set_as_top
|
Set the generated test bench module at the top in the simulation fileset where the test bench is added. |
-mode <arg>
|
Specifies simulation mode. Allowed values are behavioral, post-synthesis, or post-implementation. The default is behavioral. |
-type <arg>
|
Specifies simulation type. Allowed values are functional or timing (not applicable for behavioral mode). |
-force
|
Overwrite existing test bench file. |
-quiet
|
Execute the command quietly, returning no messages from the command.
The command also returns TCL_OK regardless of any errors encountered
during execution. Note: Any errors encountered on the command line while launching the
command are returned. Only errors occurring inside the command are
trapped.
|
-verbose
|
Temporarily override any message limits and return all messages from
this command. Note: Message limits can
be defined with the
set_msg_config
command. |
|
|
The following example command creates a test bench for the fifo module and adds
it to the sub_design_fifo simulation fileset:
create_testbench -name fifo -add_to_simset sub_design_fifoThe following example command generates a VCD file for the /top/DUT/fifo/buf_1 instance of the buf module. It
records waveform activity for 2000 ns and then, closes the VCD file handle. Next, it
creates a test bench with a module named tb, adds the test bench to the
test_buffer simulation fileset, and sets
tb as top module in this fileset:
generate_vcd_ports {/top/DUT/fifo/buf_1}
run 2000ns
close_vcd -ports
create_testbench -name tb -add_to_simset test_buffer -set_as_top