Xcelium Simulator Compilation Options - 2025.2 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2025-12-17
Version
2025.2 English
Table 1. Xcelium Compilation Options
Options Description
Verilog Options Specify compilation options for Verilog files
Generics/Parameters options Specify Generics/Parameters
xcelium.compile.tcl.pre Specify pre-compile step Tcl hook
xcelium.compile.v93 Enable VHDL-93 features
xcelium.compile.relax Enable relaxed VHDL interpretation
xcelium.compile.load_glbl Load GLBL module
xcelium.compile.xmvhdl.more_options More XMVHDL compilation options
xcelium.compile.xmvlog.more_options More XMVLOG compilation options
xcelium.compile.xmsc.more_options More XMSC compilation options
xcelium.compile.g++.more_options More G++ compilation options
xcelium.compile.gcc.more_options More GCC compilation options