Vivado Simulator Elaboration Options - 2024.2 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-11-13
Version
2024.2 English
Table 1. Vivado Simulator Elaboration Options
Option Description
xsim.elaborate.snapshot Specifies the simulation snapshot name
xsim.elaborate.debug_level Choose simulation debug visibility level. By default, it is typical
xsim.elaborate.relax Relax strict HDL Language checking rules
xsim.elaborate.mt_level Specify the number of sub-compilation jobs to run in parallel
xsim.elaborate.load_glbl Load GLBL module
xsim.elaborate.rangecheck Enables runtime value range check for VHDL
xsim.elaborate.sdf_delay Specifies sdf timing delay type to be read for use in timing simulation
xsim.elaborate.xelab.more_options More XELAB elaboration options
xsim.elaborate.xsc.more_options More options for XSC during elaboration
xsim.elaborate.coverage.name Specify coverage database name
xsim.elaborate.coverage.dir Specify coverage database directory name
xsim.elaborate.coverage.type Specify coverage type(s) (statement branch condition toggle or all)
xsim.elaborate.coverage.library Track std/unisims/retarget libraries
xsim.elaborate.coverage.celldefine Track modules with celldefine attributes
xsim.elaborate.link.sysc Specify SystemC library to bind
xsim.elaborate.link.c Specify C/C++ library to bind