| Verilog options |
Specify compilation options for Verilog
files |
| Generics/Parameters options |
Specify Generics/Parameters |
|
xsim.compile.tcl.pre
|
Type the file path with Tcl file name containing
set of command hooks to run before the compilation starts |
|
xsim.compile.xvlog.nosort
|
Select to disable Verilog compile order
sorting |
|
xsim.compile.xvhdl.nosort
|
Select to disable VHDL compile order
sorting |
|
xsim.compile.xvlog.relax
|
Select to relax strict Verilog and SystemVerilog
language checking rules |
|
xsim.compile.xvhdl.relax
|
Select to relax strict VHDL language checking
rules |
|
xsim.compile.xsc.mt_level
|
Select the number of sub-compilation jobs to run
in parallel
- auto
- automatic
- n
- integer value greater than 1
- off
- turn off multi-threading
|
|
xsim.compile.xsc.more_options
|
Specify more XSC compilation options. Separate
the options with a space. See the xsc –help for additional options
you want to set |
|
xsim.compile.xvlog.more_options
|
Specify more XVLOG compilation options. Separate
the options with a space. See the xvlog –help for additional options
you want to set |
|
xsim.compile.xvhdl.more_options
|
Specify more XVHDL compilation options. Separate
the options with a space. See the xvhdl –help for additional options
you want to set |