VCS Simulator Compilation Options - 2025.2 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2025-12-17
Version
2025.2 English
Table 1. VCS Simulator Compilation Options
Option Description
Verilog options Specify compilation options for Verilog files
Generics/Parameters options Specify Generics/Parameters
vcs.compile.tcl.pre Specify pre-compile step Tcl hook
vcs.compile.load_glbl Load GLBL module
vcs.compile.vhdlan.more_options More VHDLAN compilation options
vcs.compile.vlogan.more_options Extra VLOGAN compilation options
vcs.compile.syscan.more_options More SYSCAN compilation options
vcs.compile.g++.more_options More G++ compilation options
vcs.compile.gcc.more_options More GCC compilation options