Using Global 3-State and Global Set and Reset Signals - Using Global 3-State and Global Set and Reset Signals - 2026.1 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2026-07-08
Version
2026.1 English

The following figure shows how Global 3-State (GTS) and Global Set/Reset (GSR) signals are used in an FPGA.

Figure 1. Built-in FPGA Initialization Circuitry Diagram X8352 User Prog r ammab le Latch/Register Global T r i-State (GTS) User Output I/O P ad Output Buff er Input Buff er User Input User T r i-State Enab le Gener al Pur pose I/Os Used f or Initialization GTS GSR User Async. Reset Global Set/Reset (GSR) Initialization Controller User Prog r ammab le Logic Resources Q D CLR C CE