Using AMD Simulation Libraries - 2025.2 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2025-12-17
Version
2025.2 English

You can use AMD simulation libraries with any simulator that supports the VHDL-93 and Verilog-2001 language standards. Certain delay and modeling information is built into the libraries to help simulate the AMD hardware devices correctly.

When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. The AMD libraries are categorized based on the model function.

The following table lists the AMD-provided simulation libraries:

Table 1. Simulation Libraries
Library Name Description VHDL Library Name Verilog Library Name
UNISIM Functional simulation of AMD primitives. UNISIM UNISIMS_VER
UNIMACRO Functional simulation of AMD macros. UNIMACRO UNIMACRO_VER
UNIFAST Fast simulation library. UNIFAST UNIFAST_VER
SIMPRIM Timing simulation of AMD primitives. N/A SIMPRIMS_VER 1
SECUREIP

Simulation library for both functional and timing simulation of AMD device features, such as the PCIe® IP, Gigabit Transceiver etc.,

You can find the list of IP's under SECUREIP at the following location:

<Vivado_Install_Dir>/data/secureip

SECUREIP SECUREIP
XPM Functional simulation of AMD primitives XPM XPM 2
  1. The SIMPRIMS_VER is the logical library name to which the Verilog SIMPRIM physical library is mapped.
  2. XPM is supported as a pre-compiled IP. Hence, you need not add the source file to the project. For third party simulators, the Vivado tools map to pre-compiled IP generated with compile_simlib.
Important: You must specify different simulation libraries according to the simulation points. There are different gate-level cells in pre- and post-implementation netlists.

The following table lists the required simulation libraries at each simulation point.

Table 2. Simulation Points and Relevant Libraries
Simulation Point UNISIM UNIFAST UNIMACRO SECUREIP SIMPRIM (Verilog Only) SDF
1. Register Transfer Level (RTL) (Behavioral) Yes Yes Yes Yes N/A No
2. Post-Synthesis Simulation (Functional) Yes Yes N/A Yes N/A N/A
3. Post-Synthesis Simulation (Timing) N/A N/A N/A Yes Yes Yes
4. Post-Implementation Simulation (Functional) Yes Yes N/A Yes N/A N/A
5. Post-Implementation Simulation (Timing) N/A N/A N/A Yes Yes Yes
Important: The Vivado simulator uses precompiled simulation device libraries. Precompiled libraries automatically update when libraries updates are installed.
Note: Verilog SIMPRIMS_VER uses the same source as UNISIM with the addition of specify blocks for timing annotation. SIMPRIMS_VER is the logical library name mapped to the Verilog physical SIMPRIM.

The following table lists the library locations.

Table 3. Simulation Library Locations
Library HDL Type Location
UNISIM Verilog <Vivado_Install_Dir>/data/verilog/src/unisims
VHDL <Vivado_Install_Dir>/data/vhdl/src/unisims
UNIFAST Verilog <Vivado_Install_Dir>/data/verilog/src/unifast
VHDL <Vivado_Install_Dir>/data/vhdl/src/unifast
UNIMACRO Verilog <Vivado_Install_Dir>/data/verilog/src/unimacro
VHDL <Vivado_Install_Dir>/data/vhdl/src/unimacro
SECUREIP Verilog <Vivado_Install_Dir>/data/secureip/

The following subsections describe the libraries in detail.