SystemVerilog Support in Vivado Simulator - SystemVerilog Support in Vivado Simulator - 2026.1 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document_ID
UG900
Release_Date
2026-07-08
Version
2026.1 English

The Vivado simulator supports the subset of SystemVerilog. The synthesizable set of SystemVerilog is listed in the following table. The supported test bench features are listed in Table 1.