Following are the supported features of VHDL 2008 (IEEE1076-2008):
| Primary Construct | Secondary Construct | LRM Section |
|---|---|---|
| Subprograms and Packages | ||
| Generic packages | Package instantiation declaration | 4.9 |
| Interface package declaration | 4.9, 6.5.5 | |
| Interface subprogram declaration | 4.2, 6.5.4 | |
| Functions as formal generic parameters | 6.5.4 | |
| Local packages (entity) | Package declaration in entity declarative part | 3.2.3, 4.7 |
| Package body in entity declarative part | 3.2.3, 4.8 | |
| Package instantiation in entity declarative part | 3.2.3, 4.9 | |
| Local packages (architecture) | Package declaration in architecture declarative part | 3.3.2, 4.7 |
| Package body in architecture declarative part | 3.3.2, 4.8 | |
| Package instantiation in architecture declarative part | 3.3.2, 4.9 | |
| Local packages (process) | Package declaration in process declarative items | 11.3, 4.7 |
| Package body in process declarative items | 11.3, 4.8 | |
| Package instantiation in process declarative items | 11.3, 4.9 | |
| Local packages (subprogram) | Package declaration inside subprogram body (procedure or function) | 4.3, 4.7 |
| Package instantiation inside subprogram body | 4.3, 4.9 | |
| Local packages (protected type) | Package declaration inside protected type body | 5.6.3, 4.7 |
| Nested packages | Package nested inside another package declaration or body | 4.7, 4.8 |
| Types | ||
| Array types | Unconstrained array of unconstrained element (arrays in ports/generics) | 5.3.2 |
| Element constraint on 2-level array | 5.3.2, 6.3 | |
| Aggregate with slice | 9.3.3.1, 8.5 | |
| Record types | Record type with unconstrained element | 5.3.3 |
| Element constraint on record element | 5.3.3, 6.3 | |
| Access types | Access type to composite (unconstrained array or record) | 5.4 |
| Protected types | Protected type declaration and body | 5.6 |
| Names | ||
| External names | External signal name | 8.7 |
| External variable name | 8.7 | |
| External constant name | 8.7 | |
| Expressions | ||
| Matching operators | Matching equality (?=) and inequality (?/=) for std_logic/vectors | 9.2.3 |
| Matching relational operators (?<, ?<=, ?>, ?>=) | 9.2.3 | |
| Maximum and minimum | Maximum operator | 5.2.6, 5.3.2.4 |
| Minimum operator | 5.2.6, 5.3.2.4 | |
| Shift operators | rol, ror, sll, srl, sla, sra | 9.2.4 |
| Unary logical reduction | Unary and, or, nand, nor, xor, xnor | 9.2.2 |
| Mixed operators | Mixing array and scalar logical operators | 9.2.2 |
| Physical type arithmetic | MOD operator for physical type (e.g., time mod time) | 9.2.7 |
| REM operator for physical type (e.g., time rem time) | 9.2.7 | |
| Static expressions | Extensions to globally static and locally static expressions | 9.4 |
| Static ranges and integer expressions in range bounds | 9.4 | |
| Sequential Statements | ||
| Sequential signal assignment | Sequential conditional signal assignment | 10.5.3 |
| Sequential selected signal assignment | 10.5.4 | |
| Case statement | Matching case statement | 10.9 |
| Concurrent Statements | ||
| Concurrent signal assignment | Matching selected signal assignment (with expression select ?) | 11.6 |
| Generate statement | If-else-if generate | 11.8 |
| Case generate | 11.8 | |
| Process statement | Process (all) statement -- simplified sensitivity list | 11.3 |
| Declarations and Miscellaneous | ||
| Port and signal | Reading output ports | 6.5.2 |
| Expressions in port maps | 6.5.7 | |
| Generics | Referencing generics in generic lists | 6.5.1 |
| Generic types in entities | 6.5.3 | |
| Functions | Relaxed return rules for function return values | 10.13 |
| Unconstrained types | Unconstrained element types | 5.3.2 |
| Predefined types | boolean_vector and integer_vector array types | 5.3.2, 16.3 |
| Lexical | Block comments | 15.9 |
| Context | Context declaration | 13.3 |
Note: For detailed information about
features, see Supported VHDL-2008 Features section in
Vivado
Design Suite User Guide: Synthesis (UG901).