Following are the supported features of VHDL 2019:
| Primary construct | Secondary construct | LRM section |
|---|---|---|
| Subprograms and packages | Impure function -- signal in formal parameter | 4.2.2.1 |
| Impure function -- signal out formal parameter | 4.2.2.1 | |
| Impure function -- signal inout formal parameter | 4.2.2.1 | |
| Reading out port via impure function | 4.2.2.1, 6.5.2 | |
| Generic clause on subprogram (generic subprograms) | 4.2, 4.2.2.2 | |
| Variable formal parameter in generic subprogram | 4.2.2.2 | |
| Generic subprogram instantiation with generic map | 4.4 | |
| Function return subtype inferred from context | 4.2.1 | |
| Types | INTEGER is 64-bit two's complement (was 32-bit) | 5.2.3.1 |
| Anonymous integer base type identity | 5.1, 5.2.3.1 | |
| Anonymous physical base type identity | 5.1, 5.2.4.1 | |
| Empty record type (record with no elements) | 5.3.3 | |
| Empty record as port type | 5.3.3 | |
| Protected type with generic clause | 5.6 | |
| Protected type as subprogram parameter | 5.6 | |
| Protected type as element of composite type (array/record) | 5.6 | |
| Declarations | Subtype inferred from initial value (variable/constant/signal) | 6.4 |
| Reference prior port elements in port declaration | 6.5.2, 6.5.6.1 | |
| Interface mode view definition for record types | 6.5.2 | |
| Partial connections in port maps | 6.5.2 | |
| Optional trailing semicolon in interface list | 6.5.6.1 | |
| Generic subprogram association rules | 6.5.6.2 | |
| Regularized component declarations | 6.8 | |
| Expressions | Conditional expression | 9.1 |
| Conditional return (return when condition) | 10.13 | |
| Predefined language environment | Array index subtype attribute (A’INDEX) | 16.2.3 |
| Range record attributes (R’RECORD, R’VALUE) | 16.2.6 | |
| Environment API (TOOL_NAME, TOOL_VERSION, conditional analysis identifiers) | 16.5.6 | |
| Tool directives | Conditional analysis directives (`if / `elsif / `else / `end) | 24.2 |