Running VHDL 2019 in Standalone or Prj Mode - 2025.1 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2025-05-29
Version
2025.1 English

To compile a file only with VHDL 2019 mode, you need to use -2019 switch to xvhdl.

For example, to compile a design called top.vhdl in VHDL-2019, the following command line can be used:

xvhdl -2019 -work mywork top.vhdl

The Vivado simulator executable xelab is used to elaborate a design and produce an executable image for simulation.

xelab can do either of the following:

  • Elaborate on parser dumps produced by xvhdl
  • Directly use vhdl source files.

No switch is needed to elaborate on parser dumps produced by xvhdl. You can use -vhdl2019 to xelab to directly use vhdl source files.

Example 1:

xelab top -s mysim; xsim mysim -R

Example 2:

xelab -vhdl2019 top.vhdl top -s mysim; xsim mysim -R

Instead of specifying VHDL files in the command line for xvhdl and xelab, a .prj file can also be used. If you have three files for a design called top.vhdl (2019 mode), bot1.vhdl(2018 mode), and bot.vhdl (93 mode), you can create a project file named example.prj as follows:

vhdl xil_defaultlib bot.vhdl
vhdl2018 xil_defaultlib bo1t.vhdl
vhdl2019 xil_defaultlib top.vhdl

In the project file, each line starts with the language type of the file, followed by the library name such as xil_defaultlib and one or more file names with a space separator. For VHDL 93, use vhdl as the language type. For VHDL 2008, use vhdl2008 while for VHDL 2019 use vhdl2019 instead.

A .prj file can be used as shown in the example below:

xelab -prj example.prj xil_defaultlib.top -s mysim; xsim mysim -R

Alternatively, to mix VHDL 93, VHDL 2008, and VHDL 2019 design units, compile the files separately with a proper language mode specified to xvhdl. Then, elaborate on top(s) of the design. For example, if you have a VHDL 93 module called bot in file bot.vhdl, a VHDL-2008 module called bot1 in file bot1.vhdl, and a VHDL-2019 module called top in file top.vhdl, you can compile them as shown in the example below:

xvhdl bot.vhdl
xvhdl -2008 bot1.vhdl
xvhdl -2019 top.vhdl
xelab -debug typical top -s mysim

Once the executable is produced by xelab, you can run the simulation as usual.

Example 1:

xsim mysim -gui

Example 2:

xsim mysim -R