Questa Advanced Simulator Simulation Options - 2025.2 English - UG900

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2025-12-17
Version
2025.2 English
Table 1. Questa Advanced Simulator Simulation Options
Option Description
questasim.simulate.tcl.post Type the file path and the name containing the Tcl file with a set of command hooks to run after the simulation ends.
questasim.simulate.runtime Specify simulation runtime
questasim.simulate.log_all_signals Select to log simulation output for viewing specified HDL objects
questasim.simulate.custom_do Type the file path and the name of the custom do file to source instead of default do file.
questasim.simulate.custom_udo Type the file path and the name of the custom udo file to source instead of default udo file.
questa.simulate.custom_wave_do Type the file path and the name of the custom wave do file to source instead of default wave do file.
questasim.simulate.sdf_delay Specify the delay type for sdf annotation
sdfmin
use the minimum delay
sdfmax
use the maximum delay
questa.simulate.ieee_warning Select to suppress IEEE warnings
questasim.simulate.saif Type the file path and the name of the SAIF file. The SAIF file provides information about transitions in a digital circuit. This data helps with power estimation and optimization.
questasim.simulate.saif_scope Type the file path and the name of the design hierarchy instance name for which power estimation is needed.
questasim.simulate.sc_async_update Select to enable asynchronous request updates for SystemC.
questasim.simulate.vsim.more_options Specify more VSIM simulation options. Separate the options with a space. See the vsim –help for additional options you want to set.