| Verilog options |
Specify compilation options for Verilog files |
| Generics/Parameters options |
Specify Generic/Parameters |
| questasim.compile.tcl.pre |
Type the file path with Tcl file name containing set of command hooks to run
before the compilation starts |
| questasim.compile.vhdl_syntax |
Select the VHDL syntax standard |
| questasim.compile.use_explicit_decl |
Select to log all signals |
| questasim.compile.load_glbl |
Select to load GLBL module |
| questasim.compile.vlog.more_options |
Specify more VLOG compilation options. Separate the options with a space. See
the vlog –help for additional options you want to set |
| questasim.compile.vcom.more_options |
Specify more VCOM compilation options. Separate the options with a space. See
the vcom –help for additional options you want to set |
| questasim.compile.sccom.cores |
Specify the number of process cores to run in parallel |
| questasim.compile.sccom.more_options |
Specify more SCCOM compilation options. Separate
the options with a space. See the sccom –help for additional options
you want to set |