The dedicated Global 3-State (GTS) net drives output buffers to a high-impedance state during configuration. This net operates alongside the dedicated Global Set/Reset (GSR) signal. All general-purpose outputs are affected whether they are regular, 3-state, or bidirectional outputs during normal operation. This ensures that the outputs do not erroneously drive other devices as the FPGA is configured.
In simulation, the GTS signal is usually not driven. The circuitry for driving GTS is available in the post-synthesis and post-implementation simulations. GTS can be optionally added for the pre-synthesis functional simulation, but the GTS pulse width is set to zero by default.