Register Transfer Level (RTL) behavioral simulation can include:
- RTL Code
- Instantiated UNISIM library components
- Instantiated UNIMACRO components
- UNISIM gate-level model (for the Vivado logic analyzer)
- SECUREIP Library
RTL behavioral simulation lets you simulate and verify your design prior to any translation made by synthesis or implementation tools. You can verify your designs as a module or an entity, a block, a device, or a system.
You typically perform RTL behavioral simulation to verify your code syntax and confirm that your code functions as intended. This step describes the design in RTL, so no timing information is required.
RTL behavioral simulation is not architecture-specific unless the design contains an instantiated device library component. To support instantiation, AMD provides the UNISIM library.
When you verify your design at the behavioral RTL, you can fix design issues earlier and save design cycles.
Keeping the initial design creation limited to behavioral code allows for:
- More readable code
- Faster and simpler simulation
- Code portability (the ability to migrate to different device families)
- Code reuse (the ability to use the same code in future designs)