Hard Block Planning for Versal Adaptive SoC - 2024.2 English - UG899

In AMD Versal™ devices, gigabit transceivers (GTs) can be grouped into quads. This reduces overhead by enabling the GTs to share clocks and resets. The Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331) or the Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442) can be used to configure the GT wizard IP, which creates a wrapper around the GT*QUAD primitive. Design entry through the IP catalog and IP integrator is supported for the wizard IPs. As the IP supports GT QUAD sharing, GT Reference clock sharing and Multi_Quad GT configurations do not provide the provision to select the GT device locations.

The Hard Block Planner provides an intuitive user interface to assign GT_QUAD and REFCLK locations. The Hard Block Planner window groups GT_QUADs under Hard-IPs such as PCIe® and DCMAC. Furthermore, it provides an easy to use mechanism to assign GT_QUADs using the device sites. The Hard Block Planner provides visual feedback in the Device window for location of the REFCLK pins, the GT_QUADs and the Hard-IP blocks. It also lists the soft IPs in the design under a separate drop down menu alongside the hard IPs (highlighted in green) to facilitate the planning of its associated GT blocks. List of supported hard IPs include DCMAC, MRMAC, PCIe® , CPM, and ILKN.

Once you open a synthesized design, it reads and processes netlist objects and collects all hard-IPs available in a design. This planner allows you to cross-probe the location in Device window view for changing or assigning the Site. The Hard Block Planner option in the Windows menu appears only once you open a synthesized design or implemented design. Hard Block Planner window has three buttons on top (highlighted in red). The first button on the left marks all hard blocks in blue, all associated GTs in red and the REFCLK sources in green. The button in the middle does the same for a selected IP group. The last button on the right removes the marks from all items to clear up the device view. These buttons can be used to quickly glance the relative placement of IPs and their associated GT in Device View. The SoftIPs section shows the GT Parent IP instance and the associated GTs.

The previous figure is the hard block planner for a design using the Versal adaptive SoC transceivers wizard subsystem to configure the GTs. It shows two sections:

HardIPs

Lists the GTs associated with the hard blocks.

SoftIPs

Lists in order all GTs that have the RESET_DONE pins connected in a daisy chain manner, as a single group named GT grouping n, where n shows the group number.

You can choose the GT locations from the drop down in the site column in the same order as its listed, where the first GT instance in the list is of highest order.