Designing with System Verilog - 2025.2 English - UG896

Vivado Design Suite User Guide: Designing with IP (UG896)
Document ID
UG896
Release Date
2025-12-17
Version
2025.2 English

The support for System Verilog wrappers has been added from 2025.2 release onwards. System Verilog wrapper support for BD and .xci files involves enabling tools and features that allow for the creation and customization of HDL wrappers in System Verilog for Block Designs (BD) and Intellectual Property (IP) .xci files. Here are the key details:

GUI Updates

  • The GUI for generating System Verilog wrappers has been enhanced in Vivado to include options for wrapper generation across different types, including System Verilog, Verilog, and VHDL.
  • The Create HDL Wrapper dialog has been updated to support System Verilog as one of the languages to generate wrapper. Target language options are dynamically customizable based on user selections.

In previous builds, the Create HDL Wrapper dialog in Vivado used to support Verilog and VHDL but used to not allow the user to generate System Verilog wrappers for BDs. This lack of support limited flexibility and prevented streamlined integration with modern workflows that involve System Verilog interfaces.

Dialog Box Updates

BD Updates: The Create HDL Wrapper dialog will be revamped to support System Verilog wrappers for BDs.

Figure 1. Create HDL Wrapper

Below is the functionality:

Checkbox Feature: Generated wrapper will be used as Top Module.

When Checked: The wrapper’s language will default to the target language defined in the Project Settings > General > Target Language.

When Unchecked: Users can manually select the language for wrapper generation from three options:

  • System Verilog
  • Verilog
  • VHDL

Dropdown Language Selection: Dynamically enabled based on checkbox state:

  • Default Behavior: Displays the current target language.
  • Custom Selection: Allows manual choice of preferred language.

Workflow Integration

  • Allows easy navigation between Project Settings to adjust target language and the Create HDL Wrapper dialog.
  • Support dynamic generation of wrapper files using Tcl commands executed in the backend:
    make_wrapper -language system_verilog -inst_template [get_files my_bd.bd]

System Verilog Wrapper will have an extension (*_sv.sv).

Figure 2. Example System Verilog Generated Wrapper

System Verilog Wrapper (*_sv.sv) content:

  • File registered using ‘add_files’ command (for example, ‘add_files c:/path/to/project_1.gen/sources_1/ip/my_ip/my_ip_sv.sv’)
  • File sourced directly from IP/BD generation directory (for example, c:/path/to/project_1.gen/sources_1/ip/my_ip/my_ip_sv.sv)
  • Wrapper will automatically update when IP or BD is regenerated, when the file is rewritten in place.
Note: System Verilog cannot be used as Top level wrapper.

Updates for .xci

Figure 3. Create HDL Wrapper for .xci

Tcl commands to generate the wrapper:

The make_wrapper command in Vivado plays a critical role in generating HDL wrappers for different components like Block Design (BD), .xci, and .xcix files. Here are the key details about the command and how it is used.

Command Overview (TCL)

The make_wrapper command is used to generate wrapper files in different HDL languages. With the addition of System Verilog support, make_wrapper now includes options for generating System Verilog wrappers and templates for both BD and .xci/.xcix files.


copy .srcs checked ->import
make_wrapper [get_files
my_ip.xci] -language systemverilog -import

Uncheck copy .srcs
-> add
make_wrapper [get_files
my_ip.xci] -language systemverilog -add

import_files
/path/to/sources/top.sv

set_property top
"top" [current_fileset]
Note: The make_wrapper command is integrated with the Vivado GUI. When right-clicking on a BD, .xci, or .xcix file, the "Create HDL Wrapper" option invokes the command.
Note: Core container should be enabled for the IP to create .xcix version and then the make_wrapper command should be used for the .xci core.

Instantiation templates .sveo for BD and XCI

The .sveo file is a System Verilog instantiation template file generated by Vivado. The .sveo file includes pre-configured instantiation examples for the module defined in the wrapper, making it easier for users to integrate the System Verilog wrapper into their top-level design.

Purpose of .sveo Files

  1. Quick Instantiation:
    • .sveo files provide pre-generated instantiation templates that can be directly used in your top-level System Verilog design.
    • They define the module ports, parameter values, and connection patterns for interfaces such as AXI Memory Mapped or AXI Streaming.
  2. Improved Workflow Integration:
    • Eliminates manual effort in creating instantiation code for wrappers.
    • Ensures consistency across instances generated from block designs (BDs) or IP cores.
  3. Usage for System Verilog Wrappers:
    • When creating wrappers for BDs or .xci/.xcix files, .sveo files are automatically generated alongside the wrapper files.
  4. Benefits:
    • Time-Saving: Reduces the effort required to instantiate complex modules manually.
    • Consistency: Ensures that instances are accurately parameterized and connected, avoiding errors in integration.
    • Ease of Debugging: Provides standard instantiations that simplify the debugging process during simulation and synthesis.

Tcl command: make_wrapper -language system_verilog -inst_template [get_files my_ip.xci].

Generated Files:

Location: project_1/project_1.gen/sources_1/ip/axi_bram_ctrl_1/axi_bram_ctrl_1_sv.sveo.

Common Scenarios

  1. Block Design (BD) Integration:
    • When generating wrappers for BDs, .sveo templates simplify the use of System Verilog instances by defining how the module fits into the top-level design.
  2. In IP Flows:
    • .sveo templates standardize instantiations for Xilinx IP such as AXI block RAM Controller or AXI DMA.

Path:./project_1.gen/sources_1/ip/my_ip/my_ip_sv.sveo

System Verilog XPM

From this release, SV XPMs are included in Language Template section of Vivado.

In Vivado 2025.2, System Verilog (SV) templates are integrated into the "Language Template" section as part of efforts to streamline the design and instantiation workflow for Xilinx Parameterized Macros (XPMs).

Currently, System Verilog templates for XPM modules like xpm_noc, xpm_fifo, or xpm_memory are included under Tools > Language Templates > System Verilog.

Templates will include:

  • Module Definitions: For quick instantiation into RTL designs.
  • Interface Definitionss: Pre-configured ports aligned with Vivado's AXI interfaces (AXI MM, AXI Lite, AXI Stream).
  • Automation in Vivado: The tool will auto-detect the use of XPM instantiated in the RTL design and provide related templates under the System Verilog hierarchy.
  • Examples for Common Use Cases: Example SV templates such as:
    1. xpm_fifo
      • xpm_fifo_axil_sv
      • xpm_fifo_axif_sv
      • xpm_fifo_axis_sv
    2. xpm_noc
      • xpm nmu_strm_sv
      • xpm_nsu_strm_sv
      • xpm_nmu_mm_sv
      • xpm_nsu_mm_sv

Access via Language Templates:

Navigate to Tools > Language Templates > System Verilog > XPMs in Vivado. Select the desired XPM templates for integration into your top-level design.

NOC Simulation

Simulating a Network-on-Chip (NOC) design with Vivado involves the use of System Verilog wrappers and instantiation templates. With recent enhancements, System Verilog support has been added for components such as Xilinx Parameterized Macros (XPM) and block designs (BD), simplifying NOC integration with System Verilog interfaces.

Use Case Benefits

  1. Instance Management: Easily manage user simulation wrapper and xlnoc simulation wrapper.
  2. Simplified Design Entry: Use generated templates (.sveo) for instantiation, reducing manual effort.
  3. Flexibility Across Standards: Mix System Verilog and Verilog components seamlessly in parallel top-level designs.