Vivado Naming Conventions - 2025.2 English - UG895

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID: UG895
Release Date: 2025-11-20
Version: 2025.2 English

Introduction
Overview
Navigating Content by Design Process
Launching the Vivado Design Suite in Project and Non-Project Mode
Working with Tcl
Launching the Vivado Design Suite Tcl Shell
Launching the Vivado Tools Using a Batch Tcl Script
Working with the Vivado IDE
Launching the Vivado IDE on Windows
Launching the Vivado IDE from the Command Line on Windows or Linux
Launching the Vivado IDE from the Vivado Design Suite Tcl Shell
Working with Projects
Overview
Project Types
RTL Projects
Post-Synthesis Projects
I/O Planning Projects
Imported Projects
Example Projects
Creating a Project
Creating an RTL Project
Creating a Post-Synthesis Project
Creating an I/O Planning Project
Importing an External Project
Tcl Commands for Working with Projects
Tcl Commands for Creating a Project
Tcl Commands for Importing a Project
Tcl Commands for Adding Design Sources, Constraints Files, and Simulation Sources
Tcl Commands for Adding Existing IP Sources
Tcl Commands for Setting the Project Part
Using the Vivado Design Suite Platform Board Flow
Adding User-Boards to a Repository
Using the IP Catalog with the Platform Board Flow
Using the Vivado IP Integrator with the Platform Board Flow
Managing Projects
Opening a Project
Tcl Command for Opening a Project
Opening Multiple Projects
Saving a Project
Tcl Command for Saving a Project
Closing a Project
Tcl Command for Closing a Project
Archiving Projects
Tcl Command for Archiving a Project
Working with Source Control Systems
Using the Project Summary
Configuring Project Settings
General Settings
Simulation Settings
Elaboration Settings
Synthesis Settings
Implementation Settings
Bitstream Settings
IP Settings
Tcl Command for Configuring Project Settings
Creating a Project Using a Tcl Script
Working with Source Files
Overview
Creating and Adding Design Sources
Creating New Source Files
Adding Design Sources
Specifying the Top Module and Reordering Source Files
Enabling or Disabling Source Files
Using Remote Sources or Copying Sources into Project
Updating Local Source Files
Working with IP Sources
Adding IP from the IP Catalog
Adding Existing IP Files
Tcl Command for Reporting IP Status
Generating Output Products for IP Cores
Instantiating IP Into the Design
Working with IP Integrator Sources
Creating a New Block Design
Adding Existing Block Design Sources
Tcl Command for Adding Existing Block Design Sources
Generating Output Products for Block Designs
Instantiating Block Designs into the Current Project
Working with Vitis HLS Sources
Working with Model Composer Sources
Working with System Generator Sources
Editing Source Files
Using the Find/Replace in Files Commands
Using HDL Language Templates
Using Xilinx Parameterized Macros
Enabling Xilinx Parameterized Macros
Using XPMs
Cross Probing to Source Files
Tcl Commands for Cross Probing to Source Files
Using Alternate Text Editors
Working with Simulation Sources
Adding and Creating Simulation Source Files
Working with Constraints
Adding and Creating Constraint Files
Setting the Target XDC File
Referencing Original XDC Files or Copying Files
Using Constraint Sets
Creating and Editing Constraint Sets
Defining the Active Constraint Set
Creating Constraints Sets Using the Save Constraints As Command
Exporting Constraints
Enabling or Disabling Constraint Files
Changing the Constraint Evaluation Order
Working with Sources in Non-Project Mode
RTL Analysis
Overview
Running the RTL Linter
Elaborating the Design in Project Mode
Tcl Command for Elaborating the Design in Project Mode
Viewing Elaboration Messages
Analyzing the RTL Logic Hierarchy
Exploring the Elaborated Design Schematic
Using the Hierarchy Window
Exploring the RTL Source Files
Running Methodology Checks
Running Report Methodology
Analyzing the Methodology Report
Reporting DRCs
Selecting DRC Rules
Analyzing DRC Violations
Tcl Command for Running RTL DRCs
Elaborating the Design in Non-Project Mode
Debugging the Design
Overview
RTL-Level Design Simulation
In-System Debugging
Board File
Introduction
Understanding the Platform Board Flow
Elements of the Platform Board Flow
Defining Board Files
Board
First-Level Tags in the Board File
Compatible Board Revisions
Parameters
Jumpers
Components
Parameters
Pins
Component Modes
Interfaces
Interface
Port Map
Pin Map
JTAG Chains
Connections
IP Associated Rules
IP Associated Rule
IP
Board File Linter
Steps to Use Board File Linter
Understanding Preset Files
IP_Presets
IP_Preset
IP
User Parameters
Additional Files and Special Considerations
Memory IP 7 Series Support
PS7 Presets
IP Bus Interfaces with Tri-state Ports
Ethernet Clock Handling
GT Location Constraint
IP Board Awareness
Vivado Naming Conventions
Introduction
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Training Resources
Revision History
Please Read: Important Legal Notices

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