The AMD Vivado™ Design Suite has three views of the design represented by the source files and design constraints added to the project, or read into memory in Non-Project Mode: the elaborated RTL design, the synthesized design, and the placed and routed design.
RTL elaboration of the top-level design runs RTL linting checks, performs high-level optimizations, infers logic from the RTL and builds design data structures, and optionally applies design constraints. In the default Out-of-Context design flow, you can also have the Vivado Design Suite include synthesized design checkpoints (DCPs) of IP cores, block designs, DSP modules, or hierarchical blocks into the elaborated design.
The Vivado Design Suite offers many analysis capabilities for an RTL design. For example, you can:
- RTL linting
- Visualize design details with Schematic and Hierarchy windows
- Cross probe between windows
- Run design rule checks (DRCs)
- Check messaging
- Search the RTL netlist produced with the Find command
- Create and apply constraints at the RTL level Note: You cannot run timing analysis at this stage.