In Non-Project Mode, generate output products for IP or block designs before running top-level synthesis. Configure IP to use RTL sources and constraints, or use the out-of-context (OOC) netlist from a synthesized design checkpoint in the top-level design. Be default, Vivado generates an OOC design checkpoint for each IP.
You can add IP to your design using these methods:
- Generate IP using the Vivado IP catalog
(.xci format, or .xcix for core containers).
- If an OOC design checkpoint exists in the IP directory, Vivado uses it for implementation and inserts a black box during synthesis.
- If no design checkpoint exists, Vivado uses RTL and constraint sources for global synthesis and implementation.
- Use Tcl commands to configure and generate the IP or block design. Using Tcl ensures the IP is configured, generated, and synthesized with every run.
Important: In both Project Mode and
Non-Project Mode, always use the .xci file, not the
.dcp file. This guarantees consisten use of IP output products
throughtout the design flow. If an IP is synthesized OOC and has an associated DCP, Vivado automatically uses that DCP without
re-synthesizing the IP. For more guidance, refer to the
Vivado Design Suite User Guide: Designing with
IP (UG896) and
Vivado Design Suite User Guide: Designing
IP Subsystems Using IP Integrator (UG994).