This user guide provides an overview of working with the AMD Vivado™ Design Suite to create a new design for programming into an AMD device. It provides a brief description of various use models, design features, and tool options. It explains how to prepare, implement, and manage design sources and intellectual property (IP) cores. You can follow these steps to streamline your design process.
The Vivado Design Suite lets you design, implement, and verify AMD devices in several ways. You can use the traditional register transfer level (RTL)-to-bitstream FPGA design flow described in RTL-to-Bitstream Design Flow. You can also choose system-level integration flows that focus on IP-centric design and C-based design, described in Alternate RTL-to-Bitstream Design Flows.
You can analyze and verify your design at every stage of the flow. Analysis tools include logic simulation, I/O and clock planning, power analysis, constraint definition, timing analysis, and design rule checks (DRC). You can visualize logic, adjust implementation results, program devices, and debug your design. Each tool helps you improve performance and meet design requirements.
Refer to the following resources for more information about Vivado Design Suite flows:
- Vivado Design Suite QuickTake Video: Vivado Design Flows Overview
- Vivado Design Suite QuickTake Video: Getting Started with the Vivado IDE
- Xilinx Video Training: UltraFast Vivado Design Methodology
- Vivado Design Suite Tutorial: Design Flows Overview (UG888)
You work within the Vivado Integrated Design Environment (IDE), a graphical interface that helps you assemble, implement, and validate designs and IP. You can also run all flows with Tcl commands. Write Tcl scripts to execute the entire design flow or specific parts, such as design analysis. Enter commands interactively in the Vivado Design Suite Tcl shell or Tcl Console. This flexibility lets you control the process in the way that suits you best.