You can verify Vivado IP by synthesizing it, running behavioral or structural simulations, and implementing the IP module to validate timing, power, and resource utilization. Use a small example design to validate standalone IP, or verify it within the top-level design project. Because IP creates synthesized design checkpoints, this verification strategy works well both standalone and within a project.
Many AMD IP cores in the Vivado IP catalog include an example design. To check, select the IP in the Sources area of the Manage IP or RTL project. Right-click the IP and look for Open IP Example Design. If the option is selectable, the example design is available, as shown in the figure.
You can also check using Tcl by examining the SUPPORTED_TARGETS property of the IP.
Use the Open IP Example Design right-click menu command for a selected IP to create an example design that validates the standalone IP. For more details on working with example designs and IP output products, refer to the Vivado Design Suite User Guide: Designing with IP (UG896).
Some IP include test benches with their example design, which you can use to validate customized IP functionality. You can run behavioral, post-synthesis, or post-implementation simulations. These simulations can be functional or timing based. To run timing or functional simulations, synthesize and implement the example design.
For specific information on simulating an IP, refer to the product guide for the IP. For additional simulation details, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900).