After synthesis or implementation, you can perform netlist simulation in functional or timing mode. Netlist simulation also assists with the following tasks:
- Identify post-synthesis and post-implementation functionality changes caused by:
- Synthesis attributes or constraints that create mismatches (such as full_case and parallel_case)
- UNISIM attributes applied in the Xilinx Design Constraints (XDC) file
- Differences in language interpretation between synthesis and simulation
- Dual-port RAM collisions
- Missing or improperly applied timing constraints
- Operation of asynchronous paths
- Functional issues due to optimization techniques
- Sensitize timing paths declared as false or multi-cycle during STA
- Generate netlist switching activity to estimate power
- Identify X state pessimism
For netlist simulation, you can use one or more of the libraries shown in the following table.
| Library Name | Description | VHDL Library Name | Verilog Library Name |
|---|---|---|---|
| UNISIM | Functional simulation of AMD primitives | UNISIM | UNISIMS_VER |
| UNIMACRO | Functional simulation of AMD macros | UNIMACRO | UNIMACRO_VER |
| UNIFAST | Fast simulation library | UNIFAST | UNIFAST_VER |
Use the UNIFAST during functional simulation to speed up simulation runtime. UNIFAST libraries are supported only for 7 series devices. UltraScale and later device architectures do not support UNIFAST libraries because UniSim libraries already contain these optimzations by default.
For more information on AMD simulation libraries, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900). Primitives and elements in UniSim lack timing information except for clocked elements. To prevent race conditions during functional simulation, clocked elements have a clock-to-out delay of 100 ps. Waveform views can show spikes and glitches for combinatorial signals because UniSim elements have no delay for these signals.