When working in Non-Project Mode, compile your design using Tcl commands such as
read_verilog, read_vhdl, read_edif, read_ip, read_bd, and
read_xdc. Vivado orders the sources
for compilation and passes them to synthesis. For details on using the Tcl shell or
running batch scripts, refer to Working with Tcl.
Note: This section is not a complete
Tcl command reference. For full details, refer to the
Vivado
Design Suite Tcl Command Reference Guide (UG835) and
Vivado
Design Suite User Guide: Using Tcl Scripting (UG894).
| Command | Description |
|---|---|
| read_edif | Imports an EDIF or NGC netlist file into the design source fileset of the current project. |
| read_verilog | Reads the Verilog (.v) and System Verilog (.sv) source files for the Non-Project Mode session. |
| read_vhdl | Reads the VHDL (.vhd or .vhdl) source files for the Non-Project Mode session. |
| read_ip | Reads existing IP (.xci or
.xco) project files for
Non-Project Mode. For Vivado IP
(.xci), Vivado uses the synthesized design
checkpoint (.dcp) if it exists in
the IP directory for implementation. If no checkpoint exists, Vivado uses the IP RTL sources for
synthesis along with the rest of the top-level design. Vivado uses the .ngc netlist from the .xco IP project. Note:
UltraScale devices no longer support the .xco file.
|
| read_checkpoint | Loads a design checkpoint into the in-memory design. |
| read_xdc | Reads the .sdc or .xdc format constraints source files for the Non-Project Mode session. |
| read_bd | Reads existing IP integrator block designs (.bd) for the Non-Project session. |
| set_param set_property |
Used for multiple purposes. For example, it can be used to define design configuration, tool settings, and so forth. |
| link_design | Compiles the design for synthesis if netlist sources are used for the session. |
| synth_design | Launches Vivado synthesis with the design top module name and target part as arguments. |
| opt_design | Performs high-level design optimization. |
| power_opt_design | Performs intelligent clock gating to reduce overall system power. This is an optional step. |
| place_design | Places the design. |
| phys_opt_design | Performs physical logic optimization to improve timing or routability. This is an optional step. |
| route_design | Routes the design. |
| report_* | Runs a variety of standard reports, which can be run at different stages of the design process. |
| write_bitstream | Generates a bitstream file and runs DRCs. |
| write_checkpoint | Saves the design at any point in the flow. A design checkpoint consists of the netlist and constraints with any optimizations at that point in the flow as well as implementation results. |
| start_gui stop_gui |
Opens or closes the Vivado IDE with the current design in memory. |