Using Memory IP - Using Memory IP - 2026.1 English - UG892

When using AMD memory IP, complete additional I/O pin planning steps. After customizing the IP, assign top-level I/O ports to physical package pins in the elaborated or synthesized design within the Vivado IDE.

Vivado groups each memory IP port into an I/O port interface for easier identification and assignment. Use the Memory Bank/Byte Planner to assign memory I/O pin groups to byte lanes on the physical device pins. For more details, refer to the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).

If your design uses memory IP, refer to these resources:

• UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) for simulation details.
• Reference System: Kintex 7 MicroBlaze System Simulation Using IP Integrator (XAPP1180) for an example using a MicroBlaze™ processor design.