Timing Simulation - Timing Simulation - 2026.1 English - UG892

Vivado Design Suite User Guide: Design Flows Overview (UG892)
Document ID
UG892
Release Date
2026-06-23
Version
2026.1 English

AMD supports timing simulation in Verilog only. Export a netlist for timing simulation from an open synthesized or implemented design using the File > Export > Export Netlist command in the Vivado IDE. You can also use the write_verilog Tcl command. For more details, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).

The Verilog system task $sdf_annotate within the simulation netlist specifies the standard delay format (SDF) file used for timing delays. This directive appears when you enable the -sdf_anno option in the Netlist tab of the Simulation Settings dialog box in the Vivado IDE. Write the SDF file using the write_sdf command. The Vivado simulator reads the SDF file automatically during compilation.

Tip: The Vivado simulator supports mixed-language simulation. For example, if you use VHDL, you can generate a Verilog simulation netlist and instantiate it from a VHDL test bench.

Run full timing simulation to model hardware behavior accurately. This makes debugging easier if your hardware fails, as long as the timing simulation reproduces the issue.

If you skip timing simulation, make sure to do the following:

  • Confirm STA constraints are correct, paying special attention to exceptions.
  • Ensure your netlist matches your intended RTL, paying special attention to synthesis inference details.