The Vivado IDE provides a Timing Constraints wizard to guide you through creating and validating timing constraints for your design. The wizard identifies clocks and logic constructs, then lets you enter and verify constraints. It is available only in synthesized and implemented designs, because the in-memory design must be clock-aware after synthesis. For more details, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).
Tip: The Vivado Design Suite supports only Synopsys design constraints (SDC) and
Xilinx design constraints (XDC). It does not support AMD user constraints files (UCF) from the ISE Design Suite or directly
support Synplicity design constraints. For information on migrating from UCF format to
XDC format, refer to the
ISE to Vivado Design Suite Migration
Guide (UG911).