The Vivado IDE provides a Timing Constraints wizard to walk you through the process of creating and validating timing constraints for the design. The wizard identifies clocks and logic constructs in the design and provides an interface to enter and validate the timing constraints in the design. It is only available in synthesized and implemented designs, because the in-memory design must be clock aware post-synthesis. For more information, see the Vivado Design Suite User Guide: Using Constraints (UG903).
Tip: The Vivado Design Suite only supports Synopsys design constraints (SDC) and
Xilinx design constraints (XDC). It does not support AMD user constraints files (UCF) used with the ISE Design Suite nor
does it directly support Synplicity design constraints. For information on migrating
from UCF format to XDC format, see the Migrating UCF Constraints to XDC chapter in the
ISE to Vivado Design Suite Migration
Guide (UG911).