Synthesis - Synthesis - 2026.1 English - UG892

You can use Vivado synthesis to perform a global, top-down synthesis of your complete RTL design. By default, Vivado uses an out-of-context (OOC) bottom-up design flow. This flow synthesizes IP cores from the AMD IP catalog and block designs from the IP integrator.

You can also synthesize specific modules of a hierarchical RTL design as OOC modules. This OOC approach lets you synthesize, implement, and analyze design modules, IP cores, or block designs independently from the top-level design. Vivado stores the OOC synthesized netlist and uses it during top-level implementation to preserve results and reduce runtime.

The OOC flow efficiently supports hierarchical team design, IP and IP subsystem synthesis and implementation. It also supports managing large, complex design modules. Vivado supports third-party synthesized netlists, such as EDIF or structural Verilog.

You must synthesize IP cores from the Vivado IP catalog using Vivado synthesis. Exceptions include memory IP for 7 series devices. For details, refer to the IP-specific data sheet. For more information on the OOC design flow, refer to Out-of-Context Design Flow.