The Vivado Design Suite supports FPGA logic synthesis tools from Synopsys and Mentor Graphics. In Vivado, you can import synthesized netlists in structural Verilog or EDIF format for implementation. You can also use the constraints (SDC or XDC) output by the logic synthesis tools in Vivado.
All AMD IP and block designs use Vivado synthesis. The systems does not support third-party synthesis for AMD IP or IP integrator block designs. Exceptions include certain cases such as memory IP for 7 series devices. Refer to the data sheet for a specific IP for more information.