Running Logic Synthesis and Implementation - Running Logic Synthesis and Implementation - 2026.1 English

Running Logic Synthesis and Implementation - Running Logic Synthesis and Implementation - 2026.1 English - UG892

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID

UG892

Release Date

2026-06-23

Version

2026.1 English

In Non-Project Mode, Vivado launches each implementation step with a configurable Tcl command and compiles the design in memory. Run the implementation steps in a specific order, as shown in the Non-Project Mode Tcl Script Example.

Optionally run steps such as power_opt_design or phys_opt_design when required. Instead of run strategies from Project Mode, control tool behavior with various Tcl commands. Refer to Vivado Design Suite User Guide: Implementation (UG904) for details.

Write design checkpoints after critical design steps to support analysis and constraint definition. Except for bitstream generation, design checkpoints are snapshots, not starting points for continuing the design process.

Tip: After each design step, launch Vivado IDE for interactive graphical design analysis and constraint definition on the active design. Refer to Performing Design Analysis Using the Vivado IDE for more information.