Logic simulation tools from Mentor Graphics, Cadence, Aldec, and Synopsys integrate with Vivado and can be launched directly from the IDE. You can generate netlists for all supported third-party logic simulators. From Vivado, export complete Verilog or VHDL netlists at any stage of the design flow for use with third-party simulators.
You can also export structural netlists with post-implementation delays in standard delay format (SDF) for third-party timing simulators. Vivado generates simulation scripts for enterprise users. Using these scripts and compiled libraries, you can run simulations without the Vivado environment.
Video: For more information, refer to
the Vivado Design Suite QuickTake Video: Simulating with
Cadence IES in Vivado and Vivado Design Suite QuickTake Video: Simulating with
Synopsys VCS in Vivado.
Note: Some AMD IP provides RTL sources in only Verilog or VHDL. After synthesis,
you can create structural netlists in either language.