RTL Elaboration and Analysis - 2024.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2024-05-30
Version
2024.1 English

When you open an elaborated RTL design, the Vivado IDE compiles the RTL source files and loads the RTL netlist for interactive analysis. You can check RTL structure, syntax, and logic definitions. Analysis and reporting capabilities include:

  • RTL compilation validation and syntax checking
  • Run checks to ensure your RTL is compliant with the UltraFast Methodology rules
  • Netlist and schematic exploration
  • Design rule checks
  • Early I/O pin planning using an RTL port list
  • Ability to select an object in one view and cross probe to the object in other views, including instantiations and logic definitions within the RTL source files

For more information on RTL development and analysis features, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895). For more information on RTL-based I/O planning, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).