You can specify RTL source files to create a project, then use these sources for RTL code development, analysis, synthesis, and implementation. AMD provides a library of recommended RTL and constraint templates to help you form RTL and XDC optimally for Vivado. Vivado synthesis and implementation support multiple source file types, including Verilog, VHDL, SystemVerilog, and XDC. For detailed instructions on creating and managing RTL projects, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
Refer to the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) to improve your projects. It explains proper coding and design techniques for defining hierarchical RTL sources and Xilinx design constraints (XDC). This guide also highlights Vivado Design Suite features and performance optimization strategies. By following these techniques, you can improve both design quality and programmed device performance.