By default, the Vivado Design Suite uses an out-of-context (OOC) design flow. This flow synthesizes IP from the IP catalog and block designs from the IP integrator. It lets you synthesize, implement, and analyze design modules, IP cores, or block designs independently of the top-level design. The OOC approach reduces design cycle time and eliminates design iterations, allowing you to preserve and reuse synthesis results.
IP cores from the Vivado IP catalog automatically use OOC flow. Block designs from the IP integrator also default to OOC when generating output products. For more details, refer to the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).
The Vivado Design Suite supports global synthesis and implementation. It synthesizes all modules, block designs, and IP cores as part of the integrated top-level design. You can mark specific modules or IP for OOC synthesis, and others for inclusion in the global synthesis. For block designs in the IP integrator, you can specify OOC synthesis for the entire design or for individual IP within it. In global mode, Vivado uses full design constraints, and in OOC mode, it uses estimated constraints.
The Vivado synthesis tool preserves OOC synthesis results in a cache for reuse in other designs that identical IP customization. This can significantly speed synthesis of large complex designs.
Each OCC module or IP generates a design checkpoint (DCP) containing the synthesized netlist and constraints. OOC modules appear as black boxes in the top-level design until all elements are assembled. Before opening the top-level synthesized design, reports can exclude netlist or resource details from OOC modules, creating an incomplete view.