Opening an Elaborated RTL Design - Opening an Elaborated RTL Design - 2026.1 English - UG892

Vivado Design Suite User Guide: Design Flows Overview (UG892)
Document ID
UG892
Release Date
2026-06-23
Version
2026.1 English

When you open an elaborated design, Vivado expands and compiles the RTL netlist, then applies physical and timing constraints to your target part. Vivado loads the elements into memory so you can analyze and modify the elements as needed to complete your design. For details, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

Note: Cross-module instantiation hierarchical references are not resolved by the elaborator. If you access a signal by descending into a submodule instance, such as inst.submodule.port, the elaborated schematic shows that signal as disconnected. Use explicit port connections to ensure correct visibility in the elaborated view.

The Vivado Design Suite includes linting DRCs and logic-checking tools verify correctness. You can ensure that there are no logic compilation issues, missing modules, or interface mismatches. In the Messages window, click message links to highlight problem lines in RTL files within the Vivado IDE Text Editor.

Use the Schematic window to explore logic interconnects and hierarchy. The schematic displays RTL interconnects based on RTL logic constructs. Select specific logic in the schematic to view matching RTL lines in the Vivado IDE Text Editor. For more information, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

Note: RTL elaboration does not perform FPGA technology mapping.

Constraints defined on specific logic instances, like registers, are not always resolvable during RTL elaboration because hierarchy and logic names can differ from sythesis results. Constraint mapping warnings or errors are visible during elaboration if these constrains exist. When you run synthesis, Vivado resolves these issues automatically.

Using the I/O planning capabilities of the Vivado IDE, you can interactively configure and assign I/O ports in your elaborated RTL design. You then run DRCs. Perform I/O planning after synthesis to ensure proper clock and logic constraint resolution. Post-synthesis DRCs are more extensive and help catch additional issues. For details, refer to Vivado Design Suite User Guide: I/O and Clock Planning (UG899).

Tip: When you select Report DRC, the Vivado IDE runs RTL and I/O DRCs to detect logic issues, such as asynchronous clocks and latches. For more details, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

To open an elaborated design, use one of these methods:

  • In the RTL Analysis section of the Flow Navigator, select Open Elaborated Design.
  • In the Flow Navigator, right-click RTL Analysis, and select New Elaborated Design.
  • From the menu, select Flow > Open Elaborated Design.

The default view layout for an open elaborated RTL design includes logic instances cross-selected from the schematic to specific instances in RTL source files and the elaborated RTL netlist.

Figure 1. Elaborated RTL Design View Layout