When you open a synthesized design, the Vivado Design Suite loads the synthesized netlist and applies physical and timing constraints for the target part. Vivado stores all design elements in memory so you can analyze and modify them as needed. You can save updates to constraints files, netlist, debug cores, and configuration.
In a synthesized design, perform early timing, power, and utilization estimates to check if your design meets target goals. Explore the design using various Vivado IDE windows. Objects are cross-selected across all windows. Cross probe problem lines in RTL files from windows such as Messages, Schematic, Device, Package, and Find.
Use the Schematic window to explore logic interconnect and hierarchy interactively. Apply timing constraints and perform timing analysis. Define physical constraints for I/O ports, floorplanning, or configuration interactively. For more information, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
Use the I/O planning capabilities to configure and assign I/O ports in the synthesized design. Run DRCs to identify logic issues by selecting Run DRC. Refer to the Vivado Design Suite User Guide: I/O and Clock Planning (UG899) and the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more details.
Configure and implement debug core logic in the synthesized design to support test and debug. Select signals in the Schematic or Netlist windows. Vivado configures debug cores and inserts them into the design. Core logic and interconnect are preserved through synthesis updates when possible. For more information, refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908).
To open a synthesized design, use one of the following methods:
- In the Synthesis section of the Flow Navigator, select Open Synthesized Design.
- In the Flow Navigator, right-click Synthesis, and select New Synthesized Design.
- Select .
- In the Design Runs view, double-click the run name.