You can perform design analysis and assign constraints after RTL elaboration, synthesis, or implementation. To identify design issues early, perform design analysis before implementation, including timing simulation, resource estimation, connectivity analysis, and DRCs. Open synthesis or implementation run results to perform analysis and constraint assignments. This is known as opening the design.
When you open a design, the Vivado IDE compiles the netlist and applies physical and timing constraints to the target part. You can open, save, and close designs as needed. Opening a new design prompts you to close any existing ones to preserve memory, though Vivado supports multiple open designs simultaneously.
When you open a synthesized design, the Vivado IDE displays the netlist and constraints. When you open an implemented design, the Vivado IDE displays the netlist, constraints, and implementation results. Vivado presents design data in different forms on different windows, letting you cross-probe and coordinate information between windows.
After opening a design, you can use many analysis and reporting tools in the Vivado IDE. For example, analyze device resources in graphical windows for the internal device and external physical package. You can also apply and analyze timing and physical constraints in the design using the Netlist, Device, Schematic, or Hierarchy windows.
For more information, refer to the following documents:
- Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
- Vivado Design Suite User Guide: Using Constraints (UG903)