You can choose an in-memory compilation flow, called Non-Project Mode, where you manage sources and the design process yourself. In-memory compilation applies project settings to Non-Project based designs. In this mode, you use Tcl commands or scripts to control each step, giving you full control over the flow.
When working in Non-Project Mode, Vivado reads source files from their current locations, such as a revision control system. You compile the design entirely in memory. Run each design step individually with Tcl commands, and use Tcl to set design parameters and implementation options.
You can save design checkpoints and create reports at any stage of the design process. Tailor each implementation step to meet specific design challenges, and analyze results after each design step. Open the Vivado IDE at any time for design analysis or constraints assignment.
In Non-Project Mode, you control each design step using Tcl commands. For example, it requires you to do the following:
- Rerun synthesis if you modify an HDL file after synthesis.
- Explicitly generate a timing report after routing.
- Set design parameters and implementation options using Tcl commands and parameters.
- Save design checkpoints and create reports at any stage using Tcl.
As the design flow progresses, Vivado retains the design in memory. Non-Project Mode discards the in-memory design after each session and writes data to disk only when you instruct it to. For more information on Non-Project Mode, refer to Using Non-Project Mode.