Logic Synthesis - Logic Synthesis - 2026.1 English - UG892

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2026-06-23
Version
2026.1 English

Vivado allows you to run multiple synthesis runs concurrently or serially, enabling you to find the synthesis settings that yield the best results for your design. On Linux, you can also run jobs on remote hosts, increasing your ability to explore more diverse settings.

Each synthesis run produces a separate netlist within the Vivado project directory. Opening these netlists in Vivado enables you to analyze each design, create I/O pin constraints, check timing, floorplan the device, and optionally proceed with implementation.

The most comprehensive set of DRCs is also available after the netlist is synthesized. This is the first point in the flow when the entire design is linked and Vivado has visibility of the complete netlist, including all design logic and the full clocking structure.

For more information, refer to the Vivado Design Suite User Guide: Synthesis (UG901).
Note: Running multiple jobs simultaneously on the same machine can use all the memory and cause random Vivado crashes. Reserve enough memory for all jobs running on a single machine.