The Vivado Design Suite has several logic simulation options for verifying designs or IP. The integrated Vivado simulator lets you simulate the design, add and view signals in the waveform viewer, and debug as needed.
You can use the Vivado simulator for behavioral and structural simulation, as well as full timing simulation of implemented designs. Functional and timing simulation can be performed at various stages of the design process.
You can also use third-party simulators by generating Verilog or VHDL netlists and SDF files from the elaborated, synthesized, or implemented designs. You can configure and launch simulators from Mentor Graphics, Synopsys, Cadence, and Aldec. For details, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900).