The Vivado Design Suite supports the following established industry design standards:
- Tcl
- AXI4, IP-XACT
- Synopsys design constraints (SDC)
- Verilog, VHDL, VHDL-2008, SystemVerilog
- SystemC, C, C++
The Vivado Design Suite solution is native Tcl based and supports both SDC and Xilinx design constraints (XDC) formats. The suite extensively supports Verilog, VHDL, and SystemVerilog synthesis, making FPGA adoption easier. Vivado High-Level Synthesis (HLS) lets you define logic using native C, C++, or SystemC languages. You can use standard IP interconnect protocols such as AXI4 and IP-XACT for faster, easier system-level design integration.
By supporting these industry standards, you enable the electronic design automation (EDA) ecosystem to better integrate with the Vivado Design Suite. Many third-party tools are also integrated into the Vivado Design Suite. This compatibility and integration gives you more options for extending your design environment.