Many IP cores include XDC constraint files used during Vivado synthesis and implementation. When you customize IP from the Vivado IP catalog, Vivado applies these constraints automatically in both Project Mode and Non-Project Mode.
Many IP cores reference their input clocks in these XDC files. These clocks can originate from the top level design or from other IP cores in the design. By default, Vivado process IP clock creation and user-defined top-level clock creation early. This approach makes those clocks available to the IP cores that require them.
For more details, refer to Vivado Design Suite User Guide: Designing with IP (UG896).