You can use the C-based High-Level Synthesis (HLS) tools in the Vivado Design Suite to describe DSP functions using C, C++, and SystemC. Create and validate your C code with the Vivado HLS tools. Higher-level languages let you abstract algorithmic descriptions and specifications while exploring “what-if” scenarios with parameters to optimize design performance and device area.
HLS lets you simulate the generated RTL directly from its design environment using C-based test benches and simulation. C-to-RTL synthesis transforms your C-based design into an RTL module. You can package and implement in a larger RTL design or instantiate in an IP integrator block design.
For details on the HLS tool flow and features, refer to the following documents: