After implementation, you can program the device and analyze it with the Vivado logic analyzer or the standalone Vivado Lab Edition environment. Identify debug signals in the RTL design or insert them after synthesis, then process them throughout the flow. Add debug cores to RTL source files, the synthesized netlist, or an implemented design using the using the engineering change order (ECO) flow. Modify nets connected to a debug probe, or route internal signals to a package pin for external probing with the ECO flow. For more details, refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908).