The Vivado Design Suite supports different design entry points based on your source file types and design tasks. You can choose the project type that best fits you workflow.
- RTL Project
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- Add RTL source files and constraints
- Configure IP with the Vivado IP catalog
- Create IP subsystems with the Vivado IP integrator
- Synthesize and implement the design
- Perform design planning and analysis
- Post-Synthesis Project
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- Import third-party netlists
- Implement the design
- Perform design planning and analysis
- I/O Planning Project
- Create an empty project for use with early I/O planning and device exploration before having RTL sources.
- Imported Project
- Import existing project sources from the ISE Design Suite, Xilinx Synthesis Technology (XST), or Synopsys Synplify.
- Example Project
- Explore several example projects, including example AMD Zynq™ 7000 SoC or MicroBlaze™ embedded designs with available AMD evaluation boards.
- DFX
- Dynamically reconfigure an operating FPGA design by loading a partial bitstream file to modify reconfigurable regions of the device.